FIG. 5 is a block diagram of a conventional TFT liquid crystal display device (a display device adopting a TFT liquid crystal panel) which is a representative example of an active matrix liquid crystal display device. A member 3801 is a TFT liquid crystal panel (including common electrode (opposing electrode)), a block 3802 is a source driver made up of a plurality of source driver ICs 3802-1, 3802-2, . . . , and 3802-n (n is a natural number), a block 3803 is a gate driver made up of a plurality of gate driver ICs 3803-1, 3803-2, . . . , and 3803-m (m is a natural number), a member 3804 is a control circuit (described as controller in FIG. 5), and a member 3805 is a liquid crystal driving power supply (power supply circuit) generating voltages for driving the liquid crystal panel.
The control circuit 3804 supplies control signals such as a vertical synchronizing signal and horizontal synchronizing signal to the gate driver 3803, and supplies signals such as a horizontal synchronizing signal, start pulse signal for source driver, and data transfer clock CK to the source driver 3802. Display data supplied from the outside is converted to digital signals (R, G, and B signals) via a control circuit 3804, and fed to the source driver 3802.
FIG. 6 is a block diagram of the source driver IC 3802-1. Note that, since the other source driver ICs 3802-2 through 3802-n are identical with the source driver IC 3802-1, the descriptions thereof are omitted.
The following operations are carried out in the source driver IC 3802-1: The supplied sets of display data (R, G, and B) are latched in an input latch circuit 4401 in a time-division manner. The start pulse signal indicating the data head is transferred to a shift register circuit 4403 in sync with the data transfer clock CK, and in accordance with output signals from respective stages of the shift register circuit 4403, sampling timings of the display data are generated.
The start pulse signal transferred to the shift register circuit 4403 is supplied to the source driver IC 3802-2 which is the next stage, as a cascade output signal.
The sets of display data latched at the above-mentioned sampling timings are stored in a sampling memory 4404, as the output from the source driver IC 3802-1 (i.e. display data for one horizontal synchronizing signal). Then in sync with the horizontal synchronizing signal from the control circuit 3804 (see FIG. 5), the sets of display data having been stored are transferred from the sampling memory 4404 to a hold memory 4405, thereby being latched.
The hold memory 4404 holds the sets of display data for one horizontal synchronizing period until the input of the next horizontal synchronizing signal. The sets of display data are then supplied from the hold memory 4405 to a level shifter circuit 4406. In this level shifter circuit 4406, the signal levels of the sets of display data are shifted (typically boosted) so as to be converted to levels corresponding to the maximum driving voltage of the liquid crystal panel, and subsequently the sets of display data are fed to a D/A conversion circuit 4407.
The D/A conversion circuit 4407 selects, in accordance with the display data, one of a plurality of gradation display voltages supplied from a voltage generation circuit 4402 (which generates voltages for gradation display), and carries out digital/analog conversion.
The selected gradation display voltage is subjected to impedance lowering in an output circuit 4408, thereby being outputted from liquid crystal driving output terminals. The gradation display voltage is generated by the voltage generation circuit 4402. FIG. 11 illustrates a circuit arrangement of this voltage generation circuit 4402.
In FIG. 11, a member 2201 is a circuit generating the maximum voltage VH of the gradation display voltage (hereinafter, maximum gradation display voltage VH) and the minimum voltage VL of the gradation display voltage (hereinafter, minimum gradation display voltage VL). To this circuit 2201, an amplitude compensation voltage and offset compensation voltage obtained by adjusting, in accordance with amplitude information and offset information, variable resistors 2708 and 2709 connected externally to the source driver IC 3802-1 are inputted. These compensation voltages will be specifically described later. In accordance with the compensation voltages, the maximum gradation display voltage VH and minimum gradation display voltage VL are generated in the circuit 2201.
The voltage (VH−VL) is divided into a plurality of voltages in a resistance dividing circuit 2202 of the next stage, so that gradation display voltages (e.g. 64 gradation display voltages for 64 gradation levels) are generated. The number of gradation display voltages corresponds to the number of gradation levels required by the display panel 3801. For instance, when the display panel 3801 displays 64 gradation levels, the voltage (VH−VL) has to be divided into 64 voltages, and when the display panel 3801 displays 256 gradation levels, the voltage (VH−VL) has to be divided into 256 voltages.
In the circuit 2201 in FIG. 11, members 2705 and 2706 are low impedance conversion means which are in this case realized by voltage-follower operational amplifiers.
In the circuit 2201, the offset compensation voltage is converted to the minimum gradation display voltage VL by the voltage-follower operational amplifier 2706. Meanwhile, the amplitude compensation voltage passes through the voltage-follower operational amplifier 2706 and then is divided by resistors 2701 and 2702. A voltage produced as a result of the division is amplified by a noninversion operational amplifier 2707, and then outputted therefrom as the maximum gradation display voltage VH. The resistors 2701, 2702, 2703, and 2704 are arranged to be suitable for obtaining required voltage values.
FIG. 7 illustrates an arrangement of the TFT liquid crystal panel 3801. In the figure, a member 3901 is a pixel electrode, a member 3902 is a pixel capacity, a member 3903 is a TFT (switching element), members 3904 are source signal lines, members 3905 are gate signal lines, and a member 3906 is a common electrode (opposing electrode).
To the source signal lines 3904, gradation display voltages varying in accordance with the brightness of display pixels are supplied from the source driver 3802. To the gate signal lines 3905, scanning signals are supplied from the gate driver 3803, in order to serially turn on a vertical sequence of the TFTs 3903.
Through the TFT 3903 having been turned on, a voltage is supplied from the source signal line 3904 to the pixel electrode 3901 connected to the drain of the TFT 3903, so that an electric charge is charged in the pixel capacity 3902 between the pixel electrode 3901 and opposing electrode 3906. The voltage is held even after the TFT 3903 is turned off, so that the optical transmittance of liquid crystal is changed and gradation displaying is carried out in accordance with the change.
In liquid crystal display devices, AC driving is carried out in order to secure long-term reliability of liquid crystal, in such a manner that a voltage is converted to AC by inverting the polarity thereof at predetermined intervals, so that a DC component is cancelled. As methods of this AC conversion, the following two methods are typically used in TFT liquid crystal panels.
According to the first method, a voltage of the common electrode 3906 of the liquid crystal panel 3801 is stabilized, and a voltage (source electrode voltage in the figure) supplied to the source signal line 3904 is AC-converted in such a manner that a positive voltage and negative voltage are alternately supplied to the common electrode 3906.
FIG. 8 illustrates a driving method in accordance with the above-described first method. The figure shows the variation of a voltage supplied to one pixel. In this case, on the one hand a voltage (indicated by a dotted line in the figure) of the common electrode 3906 is stabilized, on the other hand a voltage of the source electrode (pixel electrode 3901) is varied in each frame so as to be positive or negative with respect to the common electrode 3906, so that the AC driving is carried out. Since the optical transmittance of a liquid crystal pixel is determined by an absolute value of a voltage, the voltage applied to the liquid crystal pixel in this case is |V| in all frames, and thus the optical transmittance of the pixel is always at a constant value in all frames.
According to the second method, respective voltages applied to the common electrode 3906 and source signal line 3904 of the liquid crystal panel 3801 (the voltage applied to the latter is indicated as source electrode voltage in the figure) are both varied so as to be AC-converted.
FIG. 9 illustrates a driving method in accordance with the above-described second method. This figure shows the variation of a voltage applied to one pixel, and the AC conversion is carried out in the following manner: The voltage applied to the common electrode 3906 is switched between 0 (volt) and +V (volt) in each frame of the screen, while the voltage applied to the source electrode (pixel electrode 3901) is switched between +V (volt) and 0 (volt).
When the voltage of the common electrode 3906 is 0 (volt), the voltage applied to the source electrode (pixel electrode 3901) is positive with respect to the common electrode 3906. Meanwhile, when the voltage of the common electrode 3906 is +V, the voltage applied to the source electrode is negative with respect to the common electrode 3906. In this manner, according to the second method, the voltages applied to the common electrode 3906 and source electrode, respectively, are varied so that the voltage applied to the source electrode is half as much as the voltage in the first method.
To carry out the liquid crystal driving, a voltage which is about 5V higher or lower than the voltage of the common electrode 3906 is required. The liquid crystal driving is typically carried out in such a manner that a voltage which is positive and negative with respect to the voltage of the common electrode 3906 is alternately supplied to the source electrode. According to the first method, while the display control is easily performed thanks to the stabilized voltage of the common electrode 3906, it is necessary to additionally provide a driving circuit which can generate a voltage of about 10V, in order to change the voltage for driving the source electrode (pixel electrode 3901), for instance, within the range between −5V and 5V (when the common electrode voltage is 0V) or within the range between 0V and 10V (when the common electrode voltage is 5V).
In the meantime, according to the second method, the voltage of the common electrode 3906 is varied so that the display control circuit has to be complex in structure, but a driving circuit for 5V, which is usually cheap, can be adopted. In other words, a low voltage resistant process as in the case of typical logic circuits can be adopted, thereby a high voltage resistant process not being required.
Now, the liquid crystal driving in accordance with the second method will be described. Concerning the variation of the voltage of the common electrode 3906 as in FIG. 9, FIG. 10 shows a case when an absolute value of the difference between the maximum gradation display voltage VH applied to the source electrode (pixel electrode 3901) and the voltage applied to the common electrode 3906 is not equal to an absolute value of the difference between the minimum gradation display voltage VL and the voltage applied to the common electrode 3906. In short, FIG. 10 shows a case when these absolute values have an offset. In this case, since an absolute value of the positive voltage is different from an absolute value of the negative voltage, the optical transmittance of the liquid crystal pixel varies in each frame, causing significant deterioration of display quality.
Thus, it is necessary to adjust the maximum gradation display voltage VH and minimum gradation display voltage VL so as to be equal to the level of the voltage applied to the common electrode 3906.
In connection with this, Japanese Laid-Open Patent Application No. 2000-267618 (Tokukai 2000-267618; published on Sep. 29, 2000) discloses a method of adjusting a voltage of a common electrode in order to prevent the variation of a liquid crystal driving waveform, which is caused by a voltage generated due to a parasitic capacity, from influencing on the displaying. In this manner, when an absolute value of the difference between the maximum gradation display voltage VH applied to the source electrode and the voltage applied to the common electrode is not equal to an absolute value of the difference between the minimum gradation display voltage VL and the voltage applied to the common electrode, the display quality is deteriorated.
Even after the maximum gradation display voltage VH and minimum gradation display voltage VL are modified so as to be equal to the level of the voltage applied to the common electrode, the voltage may be varied due to reasons such as noise, the adjustment of the voltages VH and VL is a very important matter.
The amplitude information and offset information have conventionally been obtained by checking the display quality by, for instance, visual observation, or by actually performing voltage measurement. Then, as in FIGS. 6 and 11, the variable resistors 2708 and 2709 connected to the outside of the source driver IC adjust the amplitude compensation voltage and offset compensation voltage, respectively, and adjust the maximum gradation display voltage VH and minimum gradation display voltage VL both applied to the source electrode. Through these operations, the improvement of the display quality has conventionally been carried out.
The foregoing description with reference to FIGS. 6 and 11 does not mention compensation voltages. It is noted here that the compensation voltages are, as described above, the amplitude compensation voltage and offset compensation voltage which compensate the state shown in FIG. 10 and cause an absolute value of a positive voltage and an absolute value of a negative voltage to be identical with each other.
Now, the operation of a conventional circuit is described with reference to FIG. 11. First, as the starting point, the maximum gradation display voltage VH and minimum gradation display voltage VL are determined as, for instance, 5V and 0V. Since this determines an amplitude voltage (=VH−VL) to be 5V, an amplitude compensation voltage is determined to be 5V and an offset compensation voltage is determined to be 0V.
An output voltage from the operational amplifier 2705 is 5V and an output voltage from the operational amplifier 2706 is 0V. Thus, provided that the resistors 2701 and 2702 have identical resistance values, a noninversion amplifier terminal (positive input terminal) of the operational amplifier 2707 receives a voltage of 2.5V. The operational amplifier 2707 and resistors 2703 and 2704 constitute a noninversion amplifier circuit, and produce an output voltage twice as much as the input voltage thereto, when the resistors 2701 and 2702 have identical resistance values. Thus, the maximum gradation display voltage VH is 5V.
Meanwhile, since a voltage equal to the voltage applied to the noninversion amplifier terminal of the operational amplifier 2706 is outputted from an output terminal of the operational amplifier 2706, the minimum gradation display voltage VL is 0V. The voltage range between the maximum gradation display voltage VH and minimum gradation display voltage VL is divided so that a plurality of gradation display voltages are generated in the resistance dividing circuit 2202.
In this case, it is desirable that the voltage applied to the common electrode has an amplitude waveform within the range of 0–5V. Thus, the description above assumes that an amplitude waveform within the range of 0.2–4.8V is applied to the common electrode. Further, in FIG. 11, assume that the resistors 2701 and 2702 have identical resistance values and the resistors 2703 and 2704 also have identical resistance values.
Since the amplitude information is 4.6V (=4.8−0.2) and the offset information is 0.2V, the variable resistor 2708 is adjusted so that the amplitude compensation voltage is varied to 4.6V, and the variable resistor 2709 is adjusted so that the offset compensation voltage is varied to 0.2V.
On the ground of the superposition principle and the relationship between the resistors 2701 and 2702, a half of the amplitude compensation voltage (4.6V), i.e. 2.3V and a half of the offset compensation voltage, i.e. 0.1V are supplied to the noninversion input terminal of the operational amplifier 2707. Then these voltages (2.3V and 0.1V) are both doubled in the operational amplifier 2707, and as the maximum gradation display voltage VH, a voltage of 4.8V is supplied from the output terminal of the operational amplifier 2707 to the resistance dividing circuit 2202. The minimum gradation display voltage VL on this occasion is 0.2V.
In this manner, the maximum gradation display voltage VH and minimum gradation display voltage VL are compensated using the amplitude information and offset information of the voltage supplied to the common electrode, so that it is possible to cause the above-mentioned positive voltage and negative voltage to have identical absolute values.
However, the above-described conventional art has the following problem.
In the conventional art described in FIGS. 6 and 11, members such as a liquid crystal driver (e.g. source driver 3802) are mounted on the display panel 3801, the display quality is checked, and then the offset compensation is carried out by adjusting the respective variable resistors 2708 and 2709. Thus, since external voltage compensation members such as the variable resistors 2708 and 2709 are required for each source driver IC, the number of components increases and hence the manufacturing costs increase.
Furthermore, the conventional art requires a mechanism for conducting the adjustment after mounting the components, and this limits the design flexibility of the module.
Moreover, since the adjustment of the offset voltage by the external voltage compensation members is required for each end product, cumbersome operations are additionally required.